CMOS-compatible lateral bipolar transistor for BiCMOS technology. II. Experimental results

For Pt.I see ibid., vol.39, no.4, p.948-51 (1992). Characteristics of a CMOS-compatible lateral bipolar transistor suitable for low-cost and high-speed BiCMOS LSIs are described. The proposed transistor has a structure analogous to that of the NMOS transistor, which employs a source and drain self-aligned structure to form an emitter and collector. The obtained values of h_FE, BV_CEO, R _CS, f_Tmax, and r_bb´, are 20, 7 V, 50 Ω, 6.3 GHz, and 450 Ω, respectively. Moreover, delay times of a two-input NAND BiCMOS gate circuit are 0.28 ns when unloaded, and 0.42 and 0.53 ns when load capacitances are 1 and 2 pF, respectively. These values are comparable to those for BiCMOS circuits using the conventional vertical bipolar transistors