Design of a 16384-bit serial charge-coupled memory device

This paper describes a 16384-bit serial charge-coupled memory device designed primarily for low cost and compatibility with existing high-volume manufacturing techniques. To obtain low access time, the device was organized as 64 recirculating shift registers each 256 bits long. Any one register can be selected at random for reading or writing, by means of a 6-bit address input. The alternatives considered in choosing the charge-coupled device (CCD) structure and chip organization are discussed. Data regeneration circuits are described in detail. The device was fabricated on a silicon chip, with an area of 2.07 mil/SUP 2//bit (including all peripheral circuitry). It operates at data rates exceeding 2 MHz, and has a minimum average access time of under 100 μs.