A Study of Single Events in GaAs SRAMs

Complementary enhancement JFET(C-EJFET) and depletion MESFET(D-MESFET) GaAs RAM cells have been simulated for single event upset. Cells were simulated using a GaAs MESFET/JFET model incorporated into SPICE. Two device locations have been determined to be vulnerable to single event hits: the gate-to-drain junction and the source-to-drain channel region. Upset caused by source-to-drain charge injection in C-EJFET cells is similar to upsets in CMOS static RAMs. Gate-to-drain charge injection not a problem in CMOS RAMs, is an additional upset mechanism in GaAs RAMs. The critical charge for such hits is lower than the source-to-drain critical charge for upset. Determination of which mechanism dominates upset requires further examination. Resistor-coupled complementary designs were studied as a possible hardening approach. The dependence of critical charge on simulated pulse decay time has also been studied. The critical charge for the unprotected GaAs SRAM upset is comparable to that of Si SRAMs of equal line widths. Finally, soft error rates have been estimated for two GaAs SRAM designs.