DocumentCode :
881462
Title :
Technology mapping algorithm targeting routing congestion under delay constraints
Author :
Shelar, Rupesh S. ; Saxena, Prashant ; Sapatnekar, Sachin S.
Author_Institution :
Enterprise Microprocessors Group, Intel Corp., Hillsboro, OR, USA
Volume :
25
Issue :
4
fYear :
2006
fDate :
4/1/2006 12:00:00 AM
Firstpage :
625
Lastpage :
636
Abstract :
Routing congestion has become a serious concern in today´s very-large-scale-integration designs. To address this, the authors propose a technology mapping algorithm that minimizes routing congestion under delay constraints in this paper. The algorithm employs a dynamic-programming framework in the matching phase to generate probabilistic congestion maps for all the matches. These congestion maps are then utilized to minimize routing congestion during the covering, which preserves the delay optimality of the solution using the notion of slack. Experimental results on benchmark circuits in a 100-nm technology show that the algorithm can improve track overflows significantly as compared to conventional technology mapping while satisfying delay constraints.
Keywords :
VLSI; dynamic programming; integrated circuit design; network routing; 100 nm; benchmark circuit; delay constraints; dynamic programming framework; probabilistic congestion maps; routing congestion minimization; technology mapping algorithm; very large scale integration design; Circuit synthesis; Delay estimation; Field programmable gate arrays; Heuristic algorithms; Integrated circuit interconnections; Minimization; Routing; Timing; Very large scale integration; Wires; Congestion estimation; delay minimization; logic synthesis; physical design; physical synthesis; placement; routing congestion; technology mapping;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2006.870078
Filename :
1610729
Link To Document :
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