43 Gb/s decision circuits in InP DHBT technology

Author

Krishnamurthy, Karthikeyan ; Chow, Jimmy ; Mensa, Dino ; Pullela, Raja

Author_Institution

Gtran Inc., Newbury Park, CA, USA

Volume

14

Issue

1

fYear

2004

Firstpage

28

Lastpage

30

Abstract

Packaged master-slave D-flip-flops designed in InP DHBT technology with 150 GHz f_t and 180 GHz f_max are presented. Measurement results using a 43.2 Gb/s nonreturn to zero (NRZ), pseudo random binary sequence (PRBS) data (generated from 4 channels of 10.8 Gb/s, 2³¹-1, PRBS data) and a 43.2 GHz clock, show a clock phase margin of 190°. 2:1 Static frequency dividers designed using the D-flip-flops have been tested up to 50 GHz and show normal operation. These circuits are key building blocks in numerous front-end circuits used for 40 Gb/s optical communication systems.

Keywords

III-V semiconductors; bipolar MIMIC; decision circuits; flip-flops; frequency dividers; high-speed integrated circuits; indium compounds; integrated circuit layout; integrated circuit packaging; 150 GHz; 180 GHz; 43.2 Gbit/s; 50 GHz; DHBT technology; InP; clock phase margin; decision circuits; front-end circuits; high-speed integrated circuits; optical communication systems; packaged master-slave D-flip-flops; pseudo random binary sequence; retimer; static frequency dividers; Binary sequences; Circuits; Clocks; DH-HEMTs; Frequency measurement; Indium phosphide; Master-slave; Optical signal processing; Packaging; Phase measurement;

fLanguage

English

Journal_Title

Microwave and Wireless Components Letters, IEEE

Publisher

ieee

ISSN

1531-1309

Type

jour

DOI

10.1109/LMWC.2003.821504

Filename

1264053