Antenna avoidance in layer assignment

Author

Wu, Di ; Hu, Jiang ; Mahapatra, Rabi N.

Author_Institution

Dept. of Comput. Sci., Texas A&M Univ., San Jose, CA, USA

Volume

25

Issue

4

fYear

2006

fDate

4/1/2006 12:00:00 AM

Firstpage

734

Lastpage

738

Abstract

The sustained progress of very-large-scale-integration (VLSI) technology has dramatically increased the likelihood of the antenna problem in the manufacturing process and calls for corresponding considerations in the routing stage. In this paper, the authors propose a technique that can handle the antenna problem during the layer-assignment (LA) stage, which is an important step between global routing and detailed routing. The antenna-avoidance problem is modeled as a tree-partitioning problem with a linear-time-optimal-algorithm solution. This algorithm is customized to guide antenna avoidance in the LA stage. A linear-time optimal jumper-insertion algorithm is also derived. Experimental results on benchmark circuits show that the proposed techniques can lead to an average of 76% antenna-violation reduction and 99% via-violation reduction.

Keywords

VLSI; integrated circuit design; network routing; trees (mathematics); VLSI; antenna avoidance; antenna effect; antenna-violation reduction; detailed routing; global routing; interconnect; layer assignment; linear-time optimal jumper-insertion algorithm; linear-time-optimal-algorithm solution; tree-partitioning problem; via-violation reduction; Computer science; Conductors; Diodes; Integrated circuit interconnections; LAN interconnection; Manufacturing processes; Plasma materials processing; Routing; Very large scale integration; Wire; Antenna effect; interconnect; layer assignment (LA); physical design; very large scale integration (VLSI);

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/TCAD.2006.870061

Filename

1610737