Title :
An image processing IC for backprojection and spatial histogramming in a pipelined array
Author :
Agi, Iskender ; Hurst, Paul J. ; Current, Wayne K.
Author_Institution :
California Univ., Davis, CA, USA
fDate :
3/1/1993 12:00:00 AM
Abstract :
The first VLSI digital signal processor that performs both high-precision image backprojection and spatial histogram calculations at raster-scan rates as high as 30 MHz is described. Realized in 1 μm CMOS technology, this 13.3 mm×13.3 mm chip is designed to handle images as large as 1024×1024 12 b pixels. Loadable coefficients and a unified architecture allow this IC to be used with a variety of computed-tomography scanners for image reconstructions, including fan- and parallel-beam reconstruction. This chip also computes the forward Radon transform, which is a spatial histogram, permitting it to be used for iterative reconstruction algorithms. The bit lengths in the fixed-point architecture assure 12 b reconstruction accuracy
Keywords :
CMOS integrated circuits; VLSI; digital signal processing chips; image processing equipment; image recognition; pipeline processing; 1 micron; 1024 pixel; 1048576 pixel; 13.3 mm; 30 MHz; CMOS; VLSI digital signal processor; backprojection; bit lengths; computed-tomography scanners; fan-beam reconstruction; fixed-point architecture; forward Radon transform; high-precision image backprojection; image processing IC; image reconstructions; iterative reconstruction algorithms; parallel-beam reconstruction; pipelined array; raster-scan rates; reconstruction accuracy; spatial histogram; spatial histogram calculations; spatial histogramming; unified architecture; CMOS technology; Computer architecture; Concurrent computing; Digital signal processors; Histograms; Image processing; Image reconstruction; Pixel; Reconstruction algorithms; Very large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of
