Title :
A 180 MHz 0.8 μm BiCMOS modular memory family of DRAM and multiport SRAM
Author :
Silburt, Allan L. ; Phillips, Richard S. ; Gibson, G. F Randall ; Wood, Steven W. ; Bluschke, Armin G. ; Fujimoto, James S. ; Kornachuk, Stephen P. ; Nadeau-Dostie, Benoit ; Verma, Rajesh K. ; Diedrich, Peter M J
fDate :
3/1/1993 12:00:00 AM
Abstract :
A family of modular memories with a built-in self-test interface designed using a synchronous self-timed architecture is described. This approach is ideally suited to modular memories embedded within synchronous systems due to its simple boundary specification, excellent speed/power performance, and ease of modelling. The basic port design is self-contained and extensible to any number of ports sharing access to a common-core cell array. The same design has been used to implement modular one-, two-, and four-part SRAMs and a one-port DRAM based on a four-transistor (4-T) cell. The latter provides a 45% core cell density improvement over the one-port SRAM. Nominal access and cycle times of 5.5 ns for 64 kb blocks have been shown for a 0.8 μm BiCMOS process with no memory process enhancements. System operation at 100 MHz has been demonstrated on a broadband time-switch chip containing 96 kb of two-port SRAM
Keywords :
BiCMOS integrated circuits; DRAM chips; SRAM chips; VLSI; built-in self test; 0.8 micron; 100 MHz; 180 MHz; 5.5 ns; 96 kbit; BiCMOS; DRAM; access time; boundary specification; broadband time-switch chip; built-in self-test interface; common-core cell array; core cell density; cycle times; ease of modelling; embedded within synchronous systems; four-port SRAM; modular memories; modular memory family; multiport SRAM; port design; speed/power performance; synchronous self-timed architecture; two-port SRAM; BiCMOS integrated circuits; Buffer storage; Built-in self-test; Digital integrated circuits; Power system modeling; Random access memory; Read-write memory; Registers; Software libraries; Switches;
Journal_Title :
Solid-State Circuits, IEEE Journal of
