300-Mc Tunnel-Diode Logic Circuits

A complete set of tunnel-diode logic circuits has been developed. The average delay per logic level is 0.5 nsec (0.5×10^¿9 sec). The average dc power dissipation per gate is 100 mw (other gate properties are given in Table I). In order to achieve this Performance, the following new techniques were employed: 1) nonlinear biasing using the tunnel resistor, a new tunneling device; 2) trimming, a technique of current bias adjustment to offset initial tolerances; 3) transmission-line terminating without sacrificing signal amplitude. Using these circuits, a 40-gate model was constructed which is capable of shifting and counting at a rate of 300 Mc. This model has been in operation for approximately 2000 hours with very good reliability.