DocumentCode
881892
Title
A 10 b 50 MHz pipelined CMOS A/D converter with S/H
Author
Yotsuyanagi, Michio ; Etoh, Toshiyuki ; Hirata, Kazumi
Author_Institution
NEC Corp., Kanagawa, Japan
Volume
28
Issue
3
fYear
1993
fDate
3/1/1993 12:00:00 AM
Firstpage
292
Lastpage
300
Abstract
A single 5 V, 10 b, 50 MHz pipelined CMOS analog-to-digital (A/D) converter with internal sample-and-hold (S/H) circuits was developed. The A/D converter features a newly developed S/H circuit with an 80 dB, 300 MHz operational amplifier, three-stage pipelined 4 b flash A/D converters with digital error correction functions, and double analog signal conversion paths whose operations are interleaved. The new A/D converter was fabricated with 0.8 μm CMOS technology
Keywords
CMOS integrated circuits; analogue-digital conversion; high definition television; sample and hold circuits; video signals; 0.8 micron; 10 bit ADC; 300 MHz; 5 V; 50 MHz; 80 dB; CMOS; S/H circuit; digital error correction functions; double analog signal conversion paths; features; flash A/D converters; internal sample-and-hold; operational amplifier; pipelined CMOS A/D converter; Analog-digital conversion; CMOS analog integrated circuits; CMOS technology; HDTV; Operational amplifiers; Sampling methods; Signal resolution; TV; Video recording; Video signal processing;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.209996
Filename
209996
Link To Document