Minimum size ROM structure compatible with silicon-gate E/D MOS LSI

Author

Kawagoe, Hiroto ; Tsuji, Nobuhiro

Volume

11

Issue

3

fYear

1976

fDate

6/1/1976 12:00:00 AM

Firstpage

360

Lastpage

364

Abstract

Describes a new read-only memory (ROM) with minimum geometry. A cascade ratioless circuit configuration is used, which is process compatible with silicon-gate metal-oxide semiconductor (MOS) large-scale integration (LSI) using depletion load MOSTs. The content of a memory cell in the new ROM is determined by the choice of the MOST threshold mode, either an enhancement or depletion mode; this differs from the conventional ROM structure where the content of a memory cell is distinguished by the thickness of gate oxide. The size of a single bit of the ROM is only 196 μm/SUP 2/ and is a reduction of 45 percent compared to a conventional silicon-gate ROM.

Keywords

Digital integrated circuits; Field effect transistors; Large scale integration; Monolithic integrated circuits; Read-only storage; Semiconductor storage devices; digital integrated circuits; field effect transistors; large scale integration; monolithic integrated circuits; read-only storage; semiconductor storage devices; Binary codes; Circuits; Decoding; Electrodes; Flip-flops; Geometry; Large scale integration; MOS devices; Power supplies; Read only memory;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.1976.1050736

Filename

1050736