A 320 MFLOPS CMOS floating-point processing unit for superscalar processors

Author

Ide, Nobuhiro ; Fukuhisa, Hiroto ; Kondo, Yoshihisa ; Yoshida, Takeshi ; Nagamatsu, Masato ; Junji, M. ; Yamazaki, Itaru ; Ueno, Kiyoji

Author_Institution

Toshiba Corp., Kawasaki, Japan

Volume

28

Issue

3

fYear

1993

fDate

3/1/1993 12:00:00 AM

Firstpage

352

Lastpage

361

Abstract

A CMOS pipelined floating-point processing unit (FPU) for superscalar processors is described. It is fabricated using a 0.5 μm CMOS triple-metal-layer technology on a 61 mm² die. The FPU has two execution modes to meet precise scientific computations and real-time applications. It can start two FPU operations in each cycle, and this achieves a peak performance of 160 MFLOPS double or single precision with an 80 MHz clock. Furthermore, the original computation mode, twin single-precision computation, double the peak performance and delivers 320 MFLOPS single precision. Its full bypass reduces the latency of operations, including load and store, and achieves an effective throughput even in nonvectorizable computations. An out-of-order completion is provided by using a new exception prediction method and a pipeline stall technique

Keywords

CMOS integrated circuits; microprocessor chips; pipeline processing; real-time systems; 0.5 micron; 160 MFLOPS; 320 MFLOPS; 80 MHz; CMOS triple-metal-layer technology; exception prediction method; floating-point processing unit; pipeline stall technique; real-time applications; superscalar processors; CMOS process; CMOS technology; Clocks; Computer applications; Delay; Memory management; Microprocessors; Out of order; Parallel processing; Reduced instruction set computing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.210003

Filename

210003