DocumentCode :
882097
Title :
Sub-1-V swing internal bus architecture for future low-power ULSIs
Author :
Nakagome, Yoshinobu ; Itoh, Kiyoo ; Isoda, Masanori ; Takeuchi, Kan ; Aoki, Masakazu
Author_Institution :
Hitachi Ltd., Tokyo, Japan
Volume :
28
Issue :
4
fYear :
1993
fDate :
4/1/1993 12:00:00 AM
Firstpage :
414
Lastpage :
419
Abstract :
A bus architecture is proposed for reducing the operating power of future ULSIs. It uses new types of bus driver circuits and bus receiver circuits to reduce the bus signal swing while maintaining a low standby current. The bus driver circuit has a source offset configuration, achieved by the use of low-VT MOSFETs and an internal supply voltage corresponding to the reduced signal swing. The bus receiver circuit has a symmetric configuration with two-level conversion circuits, each of which consists of a transmission gate and a cross-coupled latch circuit. Fast level conversion is achieved without increasing the standby current. The combination of the new bus driver and receiver enables the bus swing to be reduced to one-third that of the conventional architecture while maintaining high-speed data transmission and a low standby current. A test circuit designed and fabricated using 0.3-μm processes verifies the operation of the proposed architecture. Further improvements in the speed performance are possible with device optimization
Keywords :
CMOS integrated circuits; VLSI; digital integrated circuits; 0.3 micron; 1 V; MOSFETs; bus architecture; bus driver circuits; bus receiver circuits; cross-coupled latch circuit; high-speed data transmission; internal supply voltage; low power ULSI; low standby current; source offset configuration; symmetric configuration; two-level conversion circuits; Central Processing Unit; Circuit testing; Current supplies; Delay; Driver circuits; Latches; Power dissipation; Reduced instruction set computing; Threshold voltage; Ultra large scale integration;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/4.210023
Filename :
210023
Link To Document :
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