An 8-b 85-MS/s parallel pipeline A/D converter in 1-μm CMOS

Author

Conroy, Cormac S G ; Cline, David W. ; Gray, Paul R.

Author_Institution

Electron. Res. Lab., California Univ., Berkeley, CA, USA

Volume

28

Issue

4

fYear

1993

fDate

4/1/1993 12:00:00 AM

Firstpage

447

Lastpage

454

Abstract

A new architecture consisting of a time-interleaved array of pipelined analog-to-digital converters (ADCs) is presented. A prototype has been designed consisting of four switched-capacitor (S/C) multistage pipelined ADCs in parallel. Hardware cost is minimized by sharing resistor strings, bias circuitry and clock generation circuitry over the array. Digital error correction is employed to ease comparator accuracy requirements. Techniques are employed to minimize the effect of mismatches across the array. A key circuit issue is the design of a high-speed sample-and-hold (S/H) amplifier: a fully differential, mostly NMOS, non-folded-cascode operational-amplifier topology is used. An experimental chip was implemented in 1-μm CMOS and 8-b resolution at a sample rate of 85 megasamples per second (MS/s) was obtained. Signal-to-noise plus distortion (S/(N+D)) was 41 dB for an input sinusoid of 40 MHz

Keywords

CMOS integrated circuits; analogue-digital conversion; error correction; parallel processing; pipeline processing; switched capacitor networks; 1 micron; 40 MHz; 41 dB; 8 bit type; CMOS; NMOS nonfolded cascode; bias circuitry; clock generation circuitry; digital error correction; high-speed sample/hold amplifier; monolithic type; multistage pipelined ADCs; non-folded-cascode; operational-amplifier topology; parallel pipeline A/D converter; resistor strings; switched-capacitor; time-interleaved array; Analog-digital conversion; Circuits; Clocks; Costs; Differential amplifiers; Error correction; Hardware; Pipelines; Prototypes; Resistors;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.210027

Filename

210027