DocumentCode :
882191
Title :
Optimum load device for DMOS integrated circuits
Author :
Benz, H.F.
Volume :
11
Issue :
4
fYear :
1976
fDate :
8/1/1976 12:00:00 AM
Firstpage :
443
Lastpage :
452
Abstract :
Depletion-mode load devices can be integrated with DMOS transistors without any extra diffusions or implantation processing steps by judicious choice of the substrate crystal orientation and resistivity. For low voltage operation, <1,1,1> crystal orientation should be used. The <1,1,1> crystal orientation also yields a higher transconductance for the DMOS transistor than the <1,0,0> orientation. The geometry of the load device and the DMOS transistor can be made ratioless to conserve area. Self-aligned gates, hitherto considered incompatible with DMOS transistors, have been incorporated in the structure. The experimental DMOS invertors, using a conservative design, have achieved 4-ns propagation delay, 1.3-V operation and 2-pJ propagation delay-power dissipation product.
Keywords :
Field effect transistors; Monolithic integrated circuits; field effect transistors; monolithic integrated circuits; Circuits; Conductivity; Geometry; Inverters; Ion implantation; Low voltage; MOSFETs; NASA; Propagation delay; Transconductance;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.1976.1050757
Filename :
1050757
Link To Document :
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