Title :
Process technology for radiation-hardened CMOS integrated circuits
Author :
Dawes, William R., Jr. ; Derbenwick, Gary F. ; Gregory, B.L.
fDate :
8/1/1976 12:00:00 AM
Abstract :
A process technology for radiation-hardened CMOS integrated circuits has been defined. Process parameters for the SiO/SUB 2/ gate insulator have been optimized for radiation hardness, and circuit latch-up due to parasitic p-n-p-n structures on the integrated circuits has been prevented by gold-doping the silicon substrate to reduce carrier lifetime. The device yields for the hardened technology have been evaluated and the reliability has been characterized by bias-temperature life testing.
Keywords :
Integrated circuit production; Monolithic integrated circuits; Radiation hardening; integrated circuit production; monolithic integrated circuits; radiation hardening; CMOS integrated circuits; CMOS technology; Charge carrier lifetime; Insulation; Integrated circuit reliability; Integrated circuit technology; Integrated circuit yield; Life testing; Radiation hardening; Silicon on insulator technology;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1976.1050759
