Title :
Metallization for integrated circuits using a lift-off technique
Author :
Widmann, Dietrich W.
fDate :
8/1/1976 12:00:00 AM
Abstract :
A special lift-off technique for realizing small metal interconnection geometries for integrated circuits is described. 0.6-μm gaps between metal conductors can be obtained even at 0.8-μm metal layer thickness. The slopes of the conductors are tapered. Etching problems inherent in alloy films or sandwiched layers such as Al/Si or Al/Cu/Si are avoided by the technique proposed. SEM micrographs of Al/Si conductor patterns are presented.
Keywords :
Integrated circuit production; Metallisation; Monolithic integrated circuits; integrated circuit production; metallisation; monolithic integrated circuits; Chemicals; Conductors; Copper alloys; Geometry; Integrated circuit interconnections; Integrated circuit metallization; Resists; Semiconductor films; Silicon alloys; Sputter etching;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1976.1050760
