DocumentCode :
882321
Title :
A vertical channel JFET fabricated using silicon planar technology
Author :
Ozawa, O. ; Iwasaki, Hisao
Volume :
11
Issue :
4
fYear :
1976
Firstpage :
511
Lastpage :
518
Abstract :
A vertical channel JFET with a new structure was fabricated using a self-aligned process and doped polysilicon technology. This structure is suitable for a high power device, since many channels are easily integrated on a single chip. It is also suitable for a high frequency device, because two essential conditions for high frequency operation, sufficiently low gate resistance and small channel length, can be realized without difficulty. This device shows triode-like I-V characteristics, which are determined by the channel impurity concentration and gate diffusion profile. Typical performances of an n-channel, 4 mm/spl times/4 mm, 5520 channel power FET, designed for an audio amplifier, are a voltage amplification factor of 5, a source-to-gate breakdown voltage of 60 V, a drain-to-gate breakdown voltage of 200 V, and I/SUB DSS/=4 A at V/SUB DS/=7 V.
Keywords :
Field effect transistors; Power transistors; Semiconductor device manufacture; field effect transistors; power transistors; semiconductor device manufacture; Breakdown voltage; Doping; Electrodes; Epitaxial layers; FETs; Frequency; High power amplifiers; Impurities; Silicon; Temperature;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.1976.1050768
Filename :
1050768
Link To Document :
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