• DocumentCode
    882360
  • Title

    LSI multiplier using high speed ULG

  • Author

    Gaskill, James R., Jr. ; Flint, James H. ; Meyer, Robert G. ; Micheel, Lutz J. ; Weill, Lawrence R.

  • Volume
    11
  • Issue
    4
  • fYear
    1976
  • fDate
    8/1/1976 12:00:00 AM
  • Firstpage
    539
  • Lastpage
    544
  • Abstract
    The three-gating stage 4×4-bit multiplier design and its LSI realization using 34 ECL cascode cells are described. Use of a modular single-stage universal logic gate as the primary logic building block in the multiplier allows achievement of a factor of 2 delay reduction relative to multipliers described previously.
  • Keywords
    Digital integrated circuits; Large scale integration; Logic circuits; Multiplying circuits; digital integrated circuits; large scale integration; logic circuits; multiplying circuits; Added delay; Adders; Aerospace electronics; Airborne radar; Aircraft propulsion; Circuits; Cities and towns; Large scale integration; Logic design; Military aircraft;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.1976.1050771
  • Filename
    1050771
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=882360