Title :
A high-speed 16-kbit n-MOS random-access memory
Author :
Itoh, Kiyoo ; Shimohigashi, Katsuhiro ; Chiba, Kouetsu ; Taniguchi, Kenji ; Kawamoto, Hiroshi
Abstract :
This paper presents one version of a high-speed 16-kbit dynamic MOS random-access memory (RAM). This memory utilizes a one transistor cell with an area of 22/spl times/36 /spl mu/m/SUP 2/ which is fabricated using advanced n-channel silicon-gate MOS technology (5-/spl mu/m photolithography). The main feature of the design is a sense circuitry scheme, which allows a high speed (read access time of 200 ns) with low-power dissipation (600 mW at the 400-ns cycle time). The fully decoded memory is fabricated on a 5/spl times/7 mm/SUP 2/ chip and is assembled in a 22-lead ceramic dual-in-line package.
Keywords :
Digital integrated circuits; Monolithic integrated circuits; Random-access storage; Semiconductor storage devices; digital integrated circuits; monolithic integrated circuits; random-access storage; semiconductor storage devices; Assembly; Ceramics; Circuits; Decoding; Lithography; MOSFETs; Packaging; Random access memory; Read-write memory; Transistors;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1976.1050785
