A monostable CMOS RAM with self-refresh mode

A development of a new monostable CMOS RAM (MS/RAM) is described. A size of the MS/RAM cell, consisting of a monostable flip-flop and two interconnecting lines instead of a bistable model and three interconnecting lines, is extremely reduced. The static and dynamic behavior of the MS/RAM cell are discussed. Measurements and a computer simulation for the test device exhibited its superior performance in speed and power consumption with operating simplicity as compared with currently available large-scale memories. The test device with capacity equivalent to 1024-bit array showed an access time less than 60 ns, cycle time less than 120 ns, operating power of 40 mW, and standby power of 50 /spl mu/W in a 10-V operation. The principal advantage of MS/RAM is the static operating mode.