Title :
Three hardware architectures for the binary modular exponentiation: sequential, parallel, and systolic
Author :
Nedjah, Nadia ; Mourelle, Ld.M.
Author_Institution :
State Univ. of Rio de Janeiro
fDate :
3/1/2006 12:00:00 AM
Abstract :
Modular exponentiation is the cornerstone computation in public-key cryptography systems such as RSA cryptosystems. The operation is time consuming for large operands. This paper describes the characteristics of three architectures designed to implement modular exponentiation using the fast binary method: the first field-programmable gate array (FPGA) prototype has a sequential architecture, the second has a parallel architecture, and the third has a systolic array-based architecture. The paper compares the three prototypes as well as Blum and Paar´s implementation using the time times area classic factor. All three prototypes implement the modular multiplication using the popular Montgomery algorithm
Keywords :
field programmable gate arrays; integrated circuit design; multiplying circuits; public key cryptography; sequential circuits; systolic arrays; FPGA; Montgomery algorithm; binary modular exponentiation; fast binary method; field-programmable gate array; hardware architectures; modular multiplication; parallel architecture; public-key cryptography systems; sequential architecture; systolic array-based architecture; Adders; Computer architecture; Delay; Field programmable gate arrays; Hardware; Parallel architectures; Prototypes; Public key; Public key cryptography; Systolic arrays; Cryptography; exponentiation; modular; multiplication;
Journal_Title :
Circuits and Systems I: Regular Papers, IEEE Transactions on
DOI :
10.1109/TCSI.2005.858767
