Foreword to the Special Section on “Design for Reliability and Yield for Ultimate CMOS Technologies”

The articles in this special section focus on improving design and reliability for CMOS technologies. As technology scaling moves deeper into the nanometric domain, new fault types, severe PVT (process, voltage, and temperature) variations, and accelerated circuit aging impact adversely the fabrication yield, reliability, and life duration of electronic components. The resulting high fault rates are further being aggravated by the aggressive voltage reduction required for confining fast increasing power densities and temperatures. These trends jeopardize the lasting growth of modern silicon industry and call for efficient robust-circuit design approaches. The aim of this Special Section is to present significant recent advances on this vital topic.