Reducing branch delay to zero in pipelined processors

Author

Gonzalez, Antonio M. ; Llaberia, Jose M.

Author_Institution

Dept. of Comput. Archit., Univ. Politecnica de Catalunya, Barcelona, Spain

Volume

42

Issue

3

fYear

1993

fDate

3/1/1993 12:00:00 AM

Firstpage

363

Lastpage

371

Abstract

A mechanism to reduce the cost of branches in pipelined processors is described and evaluated. It is based on the use of multiple prefetch, early computation of the target address, delayed branch, and parallel execution of branches. The implementation of this mechanism using a branch target instruction memory is described. An analytical model of the performance of this implementation makes it possible to measure the efficiency of the mechanism with a very low computational cost. The model is used to determine the size of cache lines that maximizes the processor performance, to compare the performance of the mechanism with that of other schemes, and to analyze the performance of the mechanism with two alternative cache organizations

Keywords

buffer storage; performance evaluation; pipeline processing; branch delay; branch target instruction memory; cache lines; computational cost; delayed branch; early computation; multiple prefetch; parallel execution; performance; pipelined processors; target address; Added delay; Analytical models; Computational efficiency; Computer architecture; Concurrent computing; Costs; Hazards; Mathematical model; Pipeline processing; Prefetching;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/12.210179

Filename

210179