• DocumentCode
    883241
  • Title

    Systolic modular multiplication

  • Author

    Walter, Colin D.

  • Author_Institution
    Comput. Dept., Univ. of Manchester Inst. of Sci. & Technol., UK
  • Volume
    42
  • Issue
    3
  • fYear
    1993
  • fDate
    3/1/1993 12:00:00 AM
  • Firstpage
    376
  • Lastpage
    378
  • Abstract
    A systolic array for modular multiplication is presented using the ideally suited algorithm of P.L. Montgomery (1985). Throughput is one modular multiplication every clock cycle, with a latency of 2n+2 cycles for multiplicands having n digits. Its main use would be where many consecutive multiplications are done, as in RSA cryptosystems
  • Keywords
    digital arithmetic; multiplying circuits; systolic arrays; RSA cryptosystems; clock cycle; latency; modular multiplication; multiplicands; systolic array; Banking; Clocks; Computer graphics; Cryptography; Delay; Digital arithmetic; Hardware; Pipelines; Systolic arrays; Throughput;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/12.210181
  • Filename
    210181
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=883241