Isoplanar integrated injection logic: a high-performance bipolar technology

A newly developed technology is discussed. The emphasis of this approach is on achieving high packing density and high performance by use of various process innovations combined with topological design variations. Factors affecting packing density, DC as well as power delay product in I/SUP 2/L are analyzed and design considerations for the new structure are given. The results of computer simulations and measured device parameters and power delay are given. The following gate performance has been obtained at 100-μA injector current, βu≃2-4 for all four collectors, speed <10 ns for fan-out of four, speed <5 ns for a fan-out of one. At low currents a speed power product is 0.15 pJ. A packing density of more than 300 gates/mm/SUP 2/ including interconnect and power bussing has been achieved.