Title :
A stored charge model for estimating I/sup 2/L gate delay
Author :
Hendrickson, Thomas E. ; Huang, Jack S T
fDate :
4/1/1977 12:00:00 AM
Abstract :
Calculated results with this model compare favorably to those obtained experimentally. This model not only provides physical insight into I/SUP 2/L device operation, but serves as a useful tool for device and process design optimization.
Keywords :
Bipolar integrated circuits; Integrated logic circuits; Semiconductor device models; bipolar integrated circuits; integrated logic circuits; semiconductor device models; Delay effects; Delay estimation; Doping; Electron emission; Epitaxial growth; Propagation delay; Region 8; Semiconductor process modeling; Solid modeling; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1977.1050867
