Role of the external n-p-n base region on the switching speed of integrated injection logic (I/sup 2/L)

Two-dimensional simulation and charge control principles have been applied to reveal the factors which determine the minimum delay of an integrated injection logic (I/SUP 2/L) gate, and experimental verifications are carried out. Using a numerical analysis this paper shows that important factors in improving the speed of an I/SUP 2/L gate are reducing the amount of minority charge stored in the external base of the n-p-n transistor and use of a heavily doped emitter. It is, therefore, necessary that the concentration in the external base is increased as high as possible and that the diffusion depth is controlled with good accuracy. Improvement in speed by a factor of 2 is experimentally realized as the simulation predicts. The heavily doped external base improves upward current gain and reduces base resistance, achieving a high fan-out capability.