On the gate capacitance limits of nanoscale DG and FD SOI MOSFETs

An analytical total gate capacitance C_G model for symmetric double-gate (DG) and fully depleted silicon-on-insulator (FD/SOI) MOSFETs of arbitrary Si film is developed and demonstrated. The model accounts for the effects of carrier-energy quantization and inversion-layer screening and is verified via self-consistent numerical solutions of the Poisson and Schrödinger equations. Results provide good physical insight regarding C_G degradation due to quantization and screening governed by device structure and/or transverse electric field for nanoscale DG and FD/SOI MOSFETs. Two limits of C_G at ON-state are then derived when the silicon film t_Si approaches zero and infinity. The effect of inversion-layer screening on C_G, which is significant for ultrathin Si-film DG MOSFETs, is quantitatively defined for the first time. The insightful results show that the two-dimensional screening length for DG MOSFETs is independent of the doping density and much shorter than the bulk Debye length as a result of strong structural confinement.