Title :
Stacked I/sup 2/L circuit
Author :
Kaneko, Kenji ; Okabe, Takahiro ; Nagata, Minoru
fDate :
4/1/1977 12:00:00 AM
Abstract :
A new I/SUP 2/L circuit configuration is presented which cuts down the effective power dissipation of conventional I/SUP 2/L circuits to one third or even less. The basic idea of the new circuit concept is stacking the multiple blocks of I/SUP 2/L circuit layers and operating them in series connection.
Keywords :
Bipolar integrated circuits; Integrated logic circuits; bipolar integrated circuits; integrated logic circuits; Conductivity; Electron devices; Epitaxial layers; Equations; Laboratories; Logic circuits; Power dissipation; Resistors; Solid state circuits; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1977.1050875
