Underlap DGMOS for digital-subthreshold operation

Digital circuits operated in the subthreshold region (supply voltage less than the transistor threshold voltage) is suitable for applications requiring ultralow-power and medium frequency of operation. It is also shown that by optimizing the device structure for subthreshold operation, power dissipation can further be reduced. The impact of gate underlap on the effective gate capacitance of double-gate MOS (DGMOS) transistor for digital-subthreshold operation is analyzed in this paper. It shows that with optimum gate underlap, the parasitic fringe capacitances of DGMOS can be significantly reduced resulting in higher performance and lower power consumption. Results on a ring oscillator show that with optimum underlap, 40% improvement in delay can be achieved with 7.3 × reduction in power delay product and a 1-bit full-adder circuit can be operated at 1.25 GHz (V_dd=0.2 V) with 6.2 × less power than the one with standard (overlap) DGMOS device.