A Multi-Granularity FPGA With Hierarchical Interconnects for Efficient and Flexible Mobile Computing

Following the rapid expansion of mobile computing, mobile system-on-a-chip (SoC) designs have off-loaded most compute-intensive tasks to dedicated accelerators to improve energy and area efficiency. An increasing number of accelerators in power-limited SoCs results in large regions of “dark silicon.” Unlike processors, dedicated hardware is inflexible, so any changes would require a chip re-design, which significantly impacts cost and timeline. To address the need for efficiency and flexibility, this work presents a multi-granularity FPGA suitable for mobile computing. Occupying 20.5 mm ² in 40 nm CMOS, the chip incorporates fine-grained configurable logic blocks, medium-grained DSP processors and reconfigurable block RAMs, and two coarse-grained kernels: a 64- to 8192-point FFT processor and a 16-core universal DSP for software-defined radios. Using a mix-radix hierarchical interconnect, the chip achieves a 3-4× interconnect area reduction over commercial FPGAs for comparable connectivity, reducing overall area and leakage by 2-2.5×, and delivering up to 50% lower active power. With coarse-grained kernels, the energy efficiency reaches within 4-5× of ASIC designs.