A new multiplexed electrode-per-bit structure for a 64-kbit charge-coupled-device memory

An advanced form of the multiplexed electrode-per-bit (ME/B) structure is described for CCD memory applications. In the new structure, a merging serial register is combined with an ME/B array to make a practical and flexible CCD array. The resulting structure is called the merging ME/B (M/SUP 2/E/B). An n-channel two-level polysilicon-gate structure with ion-implanted barriers and offset CCD clocks lead to a simple rectangular layout, in addition to low power consumption. A 64-kbit CCD memory utilising the structure was designed and tested. The memory operates typically at 5-Mbits/s data rate, while a 512-bit test array is operated in less than 140-ns transfer execution time.