• DocumentCode
    883969
  • Title

    An integrated JK flip-flop circuit

  • Author

    Inabe, Yasunobu ; Katoaka, K.

  • Volume
    12
  • Issue
    4
  • fYear
    1977
  • Firstpage
    403
  • Lastpage
    406
  • Abstract
    An integrated JK flip-flop circuit, which is constructed using an RS flip-flop and four gates, is described. The circuit operation is based on an original concept, which is different from the conventional master-slave principle. Results of a monolithic integration using emitter-coupled logic (ECL) circuits are also given. As compared with the conventional master-slave-type JK flip-flop, which is constructed using ECL, a 40 percent improvement in speed-power product has been obtained.
  • Keywords
    Flip-flops; Integrated logic circuits; flip-flops; integrated logic circuits; Clocks; Complexity theory; Digital systems; Feedback; Flip-flops; Master-slave; Monolithic integrated circuits; Power dissipation; Pulse circuits; Timing;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.1977.1050921
  • Filename
    1050921
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=883969