• DocumentCode
    884053
  • Title

    A standardized approach for the reduction of LSI design time and automatic rules checking

  • Author

    Bertails, Jean-Claude ; Zirphile, Jean

  • Volume
    12
  • Issue
    4
  • fYear
    1977
  • Firstpage
    433
  • Lastpage
    436
  • Abstract
    A design method, based upon the use of standardized basic elements is proposed. A symbolic layout technique, associated with network recognition programs, enables a fast and secure design. That method has been applied to CMOS technology and practical results demonstrate its efficiency.
  • Keywords
    Circuit layout CAD; Field effect integrated circuits; Large scale integration; circuit layout CAD; field effect integrated circuits; large scale integration; CMOS technology; Circuit simulation; Circuit synthesis; Computer graphics; Design automation; Design methodology; Design optimization; Large scale integration; Layout; Routing;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.1977.1050929
  • Filename
    1050929
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=884053