DocumentCode :
884118
Title :
Hardware rip-up router with concurrent wavefront propagation
Author :
Choi, W. ; Sobelman, G.
Author_Institution :
Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
Volume :
25
Issue :
6
fYear :
1989
fDate :
3/6/1989 12:00:00 AM
Firstpage :
373
Lastpage :
374
Abstract :
The design of a hardware maze router with concurrent source/target wavefront propagation is described. The new design requires fewer clock cycles to find a shortest path than existing designs, and allows for a more efficient implementation of rip-up and reroute. Extensions to multipoint nets and multilayer carriers are included.
Keywords :
circuit layout CAD; IC layout CAD; PCB layout CAD; circuit layout CAD; concurrent wavefront propagation; efficient implementation; hardware maze router; hardware rip-up router; multilayer carriers; multipoint nets; rip-up and reroute; source/target wavefront propagation;
fLanguage :
English
Journal_Title :
Electronics Letters
Publisher :
iet
ISSN :
0013-5194
Type :
jour
DOI :
10.1049/el:19890257
Filename :
21029
Link To Document :
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