Title :
A 6-bit 3.5-GS/s 0.9-V 98-mW Flash ADC in 90-nm CMOS
Author :
Deguchi, Kazuaki ; Suwa, Naoko ; Ito, Masao ; Kumamoto, Toshio ; Miki, Takahiro
Author_Institution :
Adv. Analog Technol. Div., Renesas Technol. Corp., Itami
Abstract :
A 6-bit 3.5-GS/s flash ADC is reported. A load circuit with a clamp diode and a replica-biasing scheme is developed for low-voltage and high-speed operation. An acceleration capacitor is introduced for high-speed overdrive recovery of a comparator. An averaging and interpolation network is employed in this ADC. The interpolation factor is optimized considering random offset, active area, and systematic offset to realize low offset and small active area. The ADC is fabricated in a 90-nm CMOS process and occupies 0.15 mm2. It consumes 98 mW with a 0.9-V power supply. With Nyquist input, SNDR and SFDR at 3.5 GS/s are 31.18 dB and 38.67 dB, respectively.
Keywords :
CMOS analogue integrated circuits; CMOS digital integrated circuits; analogue-digital conversion; capacitors; interpolation; CMOS circuit; acceleration capacitor; analogue-digital conversion; clamp diode; flash ADC; high-speed overdrive comparator recovery; interpolation network; power 98 mW; replica-biasing scheme; size 90 nm; voltage 0.9 V; Acceleration; CMOS process; Calibration; Capacitors; Circuits; Clamps; Diodes; Interpolation; Preamplifiers; Sampling methods; A/D converter; ADC; active load; flash converter; interpolation; offset averaging; overdrive recovery;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2008.2004326
