Title :
An integrated test concept for switched-capacitor dynamic MOS RAM´s
Author :
Lo, T.C. ; Guidry, Mark R.
Abstract :
An approach to dynamic MOS RAM testing has been developed. This paper deals in particular with the test problems of switched-capacitor (or single-transistor) MOS RAMs. Test procedures are developed from an understanding of the technology with which the memory circuits are built. The associated design weaknesses and failure modes are first reviewed, and four simple pattern-sensitivity programs are generated. Finally, an efficient test flow is recommended for rigorous functional verification as well as design and yield improvements.
Keywords :
Field effect integrated circuits; Integrated circuit testing; Integrated memory circuits; Logic testing; Random-access storage; field effect integrated circuits; integrated circuit testing; integrated memory circuits; logic testing; random-access storage; Circuit synthesis; Circuit testing; Component architectures; Deafness; Degradation; Random access memory; Read-write memory; Space technology; Switching circuits; Test pattern generators;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1977.1050980
