Completeness of Sets of Delayed-Logic Devices

This paper concerns a property of sets of delayed-logic devices. This property, called completeness, characterizes sets of logic devices that can be used for the construction of networks to represent any finite-state machine. Associated with this property is a rate of completeness, which is the maximum input sequence rate for which any finite-state machine can be constructed from the given set of devices. Tests for completeness are presented from which the completeness or lack thereof may be determined for certain classes of sets of devices. For complete sets of devices, these tests also determine the rate of completeness.