Title :
A Diagrammatic Approach to Multilevel Logic Synthesis
Author :
Akers, Sheldon B., Jr.
Author_Institution :
Electronics Lab., General Electric Co., Syracuse, N. Y.
fDate :
4/1/1965 12:00:00 AM
Abstract :
A diagrammatic approach to the problem of synthesizing multilevel logic functions is presented. It has the advantage of giving a visual interpretation to such abstract concepts as fan-in, levels of logic, decomposition, and two-level forms.
Keywords :
Circuit synthesis; Inverters; Logic functions; Switching circuits; Upper bound;
Journal_Title :
Electronic Computers, IEEE Transactions on
DOI :
10.1109/PGEC.1965.263962
