DocumentCode
885028
Title
Bulk Processing in Distributed Logic Memory
Author
Crane, B.A. ; Githens, J.A.
Author_Institution
Bell Telephone Labs., Inc., Whippany, N. J.
Issue
2
fYear
1965
fDate
4/1/1965 12:00:00 AM
Firstpage
186
Lastpage
196
Abstract
Use of a content-addressable memory as a highly parallel digital computer is described. The ability to perform any arithmetic operation on many sets of data at the same time is shown. The memory organization and the storage of data are such that many operations are performed parallel by bit as well as parallel by word, resulting in more efficient algorithms and shorter execution times. Consideration of the limitations of a linear memory array in performing such operations leads to the description of a more efficient organization, called the two-dimensional distributed logic memory. The efficiency of this form in the bulk processing of data is illustrated by a number of algorithms for basic data processing operations, including matrix inversion.
Keywords
Arithmetic; Concurrent computing; Cranes; Data processing; Distributed computing; Flip-flops; Impedance matching; Logic arrays; Parallel processing; Pattern matching;
fLanguage
English
Journal_Title
Electronic Computers, IEEE Transactions on
Publisher
ieee
ISSN
0367-7508
Type
jour
DOI
10.1109/PGEC.1965.263964
Filename
4038398
Link To Document