Title :
A figure of merit for IC packaging
Author :
Keyes, Robert W.
fDate :
4/1/1978 12:00:00 AM
Abstract :
Powering integrated circuits is a compromise between increasing power to increase circuit speed and maintaining high packaging density while satisfying cooling constraints. The optimization of this compromise provides the basis for a packaging figure of merit.
Keywords :
Monolithic integrated circuits; Packaging; monolithic integrated circuits; packaging; Differential amplifiers; FETs; Integrated circuit packaging; Load modeling; Mirrors; Solid modeling; Solid state circuits; Transconductance; Virtual manufacturing; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1978.1051030
