• DocumentCode
    885214
  • Title

    A figure of merit for IC packaging

  • Author

    Keyes, Robert W.

  • Volume
    13
  • Issue
    2
  • fYear
    1978
  • fDate
    4/1/1978 12:00:00 AM
  • Firstpage
    265
  • Lastpage
    266
  • Abstract
    Powering integrated circuits is a compromise between increasing power to increase circuit speed and maintaining high packaging density while satisfying cooling constraints. The optimization of this compromise provides the basis for a packaging figure of merit.
  • Keywords
    Monolithic integrated circuits; Packaging; monolithic integrated circuits; packaging; Differential amplifiers; FETs; Integrated circuit packaging; Load modeling; Mirrors; Solid modeling; Solid state circuits; Transconductance; Virtual manufacturing; Voltage;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.1978.1051030
  • Filename
    1051030
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=885214