Title :
A 64-kbit dynamic MOS RAM
Author :
Arai, Eisuke ; Ieda, Nobuaki
fDate :
6/1/1978 12:00:00 AM
Abstract :
A 64-kbit dynamic MOS RAM is developed by using 2 /spl mu/m rule VLSI fabrication technology and low power circuit technology. The 2 /spl mu/m rule VLSI fabrication technology is achieved by improving various aspects of the ultraviolet photolithographic, thin-gate oxidation, arsenic ion implantation, and multilevel interconnection processes. Microminiaturization of the device structure has made the voltage requirements for its MOST threshold voltage and DC supply voltages low. A highly sensitive and low power dissipating sense circuit has been developed for the VLSI RAM. A new level-detecting circuit with a logic threshold which is independent of MOST threshold voltage is proposed. A dynamic address-buffer circuit is also shown. The fabricated 64K RAM has 200 ns of access time, 370 ns of minimum cycle time, and 150 mW of power dissipation under typical supply voltage conditions of V/SUB DD/=7 V and V/SUB BB/=-2 V.
Keywords :
Field effect integrated circuits; Integrated memory circuits; Ion implantation; Large scale integration; Photolithography; Random-access storage; field effect integrated circuits; integrated memory circuits; ion implantation; large scale integration; photolithography; random-access storage; Fabrication; Integrated circuit interconnections; Ion implantation; Logic circuits; Logic devices; Low voltage; Oxidation; Power dissipation; Threshold voltage; Very large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1978.1051049
