DocumentCode :
885451
Title :
Fast Chirplet Transform With FPGA-Based Implementation
Author :
Lu, Yufeng ; Oruklu, Erdal ; Saniie, Jafar
Author_Institution :
Electr. & Comput. Eng. Dept., Bradley Univ., Peoria, IL
Volume :
15
fYear :
2008
fDate :
6/30/1905 12:00:00 AM
Firstpage :
577
Lastpage :
580
Abstract :
This letter presents a fast chirplet transform (FCT) algorithm, a computationally efficient method, for decomposing highly convoluted signals into a linear expansion of chirplets. The FCT algorithm successively estimates the chirplet parameters in order to represent a broad range of chirplet shapes, including the broadband, narrowband, symmetric, skewed, nondispersive, or dispersive. These parameters have significant physical interpretations for radar, sonar, seismic, and ultrasonic applications. For the real-time application and embedded implementation of the FCT algorithm, an FPGA-based hardware/software co-design is developed on Xilinx Virtex-II Pro FPGA development platform. Based on the balance among the system constraints, cost, and the efficiency of estimations, the performance of different algorithm implementation schemes have been explored. The developed system-on-chip successfully exhibits robustness in the chirplet transform of experimental signals. The FCT algorithm addresses a broad range of applications including velocity measurement, target detection, deconvolution, object classification, data compression, and pattern recognition.
Keywords :
convolution; data compression; deconvolution; field programmable gate arrays; pattern recognition; signal classification; transforms; Xilinx Virtex-II Pro FPGA development platform; data compression; deconvolution; fast chirplet transform; highly convoluted signals; object classification; pattern recognition; target detection; Acoustic applications; Application software; Chirp; Dispersion; Narrowband; Parameter estimation; Radar applications; Shape; Software algorithms; Sonar applications; Detection; estimation; fast chirplet transform; field programmable gate arrays; hardware/software co-design;
fLanguage :
English
Journal_Title :
Signal Processing Letters, IEEE
Publisher :
ieee
ISSN :
1070-9908
Type :
jour
DOI :
10.1109/LSP.2008.2001816
Filename :
4639630
Link To Document :
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