• DocumentCode
    885488
  • Title

    IPP@HDL: Efficient Intellectual Property Protection Scheme for IP Cores

  • Author

    Castillo, Encarnación ; Meyer-Baese, Uwe ; García, Antonio ; Parrilla, Luis ; Lloris, Antonio

  • Author_Institution
    Univ. of Granada, Granada
  • Volume
    15
  • Issue
    5
  • fYear
    2007
  • fDate
    5/1/2007 12:00:00 AM
  • Firstpage
    578
  • Lastpage
    591
  • Abstract
    In this paper, a procedure for intellectual property protection (IPP) of digital circuits called IPP@HDL is presented. Its aim is to protect the author rights in the development and distribution of reusable modules by means of an electronic signature. The technique relies on hosting the bits of the digital signature within memory structures or combinational logic that are part of the system, at the high level description of the design. Thus, the area of the system is not increased and the signature is difficult to change or to remove without damaging the design. The technique also includes a procedure for secure signature extraction requiring minimal modifications to the system and without interfering its normal operation. The benefits of the presented procedure are illustrated with programmable logic and cell-based application-specific integrated circuit examples with several signature lengths. These design examples show no performance degradation and a negligible area increase, while probabilistic analyses show that the proposed IPP scheme offers high resistance against attacks.
  • Keywords
    application specific integrated circuits; digital circuits; industrial property; programmable logic arrays; ASIC; FPGA; IP cores; cell-based application-specific integrated circuit; digital circuits; digital signature; electronic signature; high level description; intellectual property protection scheme; probabilistic analyses; programmable logic; signature extraction; Application specific integrated circuits; Degradation; Digital circuits; Digital signatures; Intellectual property; Logic circuits; Logic design; Programmable logic arrays; Programmable logic devices; Protection; Cell-based application-specific integrated circuits (ASICs); Intellectual Property (IP) cores; field-programmable gate array (FPGA); intellectual property protection (IPP); watermarking;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2007.896914
  • Filename
    4212137