A four-point electrical measurement technique for characterizing mask superposition errors on semiconductor wafers

Data are obtained using a microelectronic van der Pauw resistor structure in conjunction with automated test, computing, and graphic display equipment. Computer-drawn vector displacement maps, equivalue contour maps, and histograms are used to display the data in a format which assists in the interpretation of sources of MSE. A six-parameter model which takes into account mask translation, rotation, and expansion is shown to fit successfully the data obtained from test wafers masked using conventional alignment equipment. A comparative evaluation of the performance of a group of aligners used for manufacturing integrated circuits is given, and an investigation of the consequences of masking silicon wafers which have been subjected to high-temperature processing is performed.