DocumentCode
885763
Title
A new high-voltage analog-compatible I/sup 2/L process
Author
Allstot, David J. ; Lui, Sik K. ; Wei, Tom S T ; Gray, Paul R. ; Meyer, Robert G.
Volume
13
Issue
4
fYear
1978
Firstpage
479
Lastpage
483
Abstract
A new technique for realizing high-performance I/SUP 2/L circuits simultaneously with high-voltage analog circuits is described. The method is flexible and may be used with any standard linear bipolar process. Only one additional noncritical masking step and one phosphorus implant are required to form the I/SUP 2/L n-wells. Experimental results are presented which show I/SUP 2/L betas of greater than eight per collector with the I/SUP 2/L BV/SUB CEO/ exceeding 3 V. The measured minimum average propagation delay is 40 ns using a 14 /spl mu/m thick, 5 /spl Omega/.cm epitaxial layer, while the analog BV/SUB CEO/ exceeds 50 V.
Keywords
Bipolar integrated circuits; Integrated circuit technology; Integrated logic circuits; Large scale integration; bipolar integrated circuits; integrated circuit technology; integrated logic circuits; large scale integration; Circuits; Conductivity; Delay; Doping; Electrons; Epitaxial layers; Forward contracts; Implants; Large scale integration; Spontaneous emission;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1978.1051080
Filename
1051080
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