DocumentCode :
885821
Title :
Substrate voltage bounce in NMOS self-biased substrates
Author :
Puri, Yogishwar
Volume :
13
Issue :
4
fYear :
1978
fDate :
8/1/1978 12:00:00 AM
Firstpage :
515
Lastpage :
519
Abstract :
The problem of substrate voltage bounce is discussed for NMOS LSI random logic designs which operate from self-biased substrates. Using chip capacitance and switching noise probability models, the impact of voltage bounce on threshold voltage variation (V/SUB T/-sigma) is illustrated and a comparison is made with designs operating from externally biased substrates. To achieve the potential performance improvement made possible through the use of substrate generators, off-chip capacitors are recommended to improve V/SUB T/-sigma control.
Keywords :
Field effect integrated circuits; Integrated circuit technology; Integrated logic circuits; Large scale integration; field effect integrated circuits; integrated circuit technology; integrated logic circuits; large scale integration; Capacitance; Coupling circuits; Impedance; Large scale integration; Logic design; MOS devices; Power supplies; Switches; Switching circuits; Threshold voltage;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.1978.1051087
Filename :
1051087
Link To Document :
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