VMOS technology applied to dynamic RAMs

A seven-mask VMOS process has been developed for dynamic RAMs with self-aligned VMOS and planar Al-gate transistors. Using 4 μm photolithography, one-transistor cells with a cell size of 150 μm/SUP 2/ have been realized. The read signal at the bit line is more than 200 mV. Implementations of a sense amplifier and a word-line driver show that those circuits determine the smallest word and bit line spacing. The paper is concluded by a proposal for a 64K RAM with a chip size of 21 mm/SUP 2/ using 4 μm design rules.