A 4K CMOS erasable PROM

Author

Chan, Yiu-Fai

Volume

13

Issue

5

fYear

1978

Firstpage

677

Lastpage

680

Abstract

A high performance ultraviolet erasable complementary MOS PROM is described. Microwatt standby power is achieved by utilizing synchronous design on an ion-implanted silicon-gate CMOS technology. The device can operate with a single voltage supply from 4 to 11 V while still maintaining TTL compatibility on all address inputs, or with two supplies allowing under 200 ns access time with both TTL compatible address and output levels. On-chip address latches and high noise immunity are some of the other features that would simplify system design using the CMOS EPROM. Programming is by avalanche injection of electrons into selected floating gates. Single-location programming and high programming duty cycle reduce programming time to less than 30 s per device.

Keywords

Field effect integrated circuits; Integrated circuit technology; Integrated memory circuits; Large scale integration; Read-only storage; Transistor-transistor logic; field effect integrated circuits; integrated circuit technology; integrated memory circuits; large scale integration; read-only storage; transistor-transistor logic; CMOS process; CMOS technology; Costs; EPROM; Energy consumption; Fabrication; PROM; Power dissipation; System-on-a-chip; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.1978.1051118

Filename

1051118